The present invention relates to a thin film transistor suitable for use in an active matrix type display apparatus and a method of fabricating the same.
Liquid crystal displays (LCD) of an active matrix type which use thin film transistors (TFTs) provide a high-quality display apparatus. There are two kinds of dot matrix type LCDs each having a plurality of pixels arranged in a matrix form: a simple matrix type and an active matrix type.
The active matrix type LCD includes pixels, pixel drive elements (active elements) and signal storage elements (storage capacitors or added capacitors) and drives a liquid crystal in a quasi-static manner which permits each pixel to store data. Each pixel drive element serves as a switch which is switched on or off in response to a scan signal. When the pixel drive element is switched on, a data signal (display signal) is transmitted via that pixel drive element to an associated display electrode, so that the liquid crystal is driven by the data signal. When the pixel drive element is disabled, the data signal is stored in the form of a charge in the associated signal storage element. The liquid crystal is kept driven by the discharging of the charge until the pixel drive element is switched on again. Even though the drive time assigned to a single pixel decreases as the number of scan lines increases, the liquid crystal is sufficiently driven. This prevents the contrast from decreasing.
TFTs are generally used as pixel drive elements. A TFT has an active layer comprised of a thin semiconductor film formed on an insulator substrate. The semiconductor film preferably includes an amorphous silicon film or a polycrystalline silicon film. A TFT having an active layer comprised of an amorphous silicon film is called an amorphous silicon TFT, while a TFT having an active layer comprised of a polycrystalline silicon film is called a polycrystalline silicon TFT. The polycrystalline silicon TFT has a greater field effect mobility and higher drive performance than the amorphous silicon TFT. Because of these advantages, the polycrystalline silicon TFT can be used as a logic circuit element as well as a pixel drive element. The use of polycrystalline silicon TFTs, therefore, allows the integration of the display screen and a peripheral drive circuit, located at the periphery of the display screen, and on the same substrate. That is, the display screen and peripheral drive circuit may be formed in the same step.
FIG. 1 is a schematic block diagram of a typical active matrix type LCD. The LCD includes a display panel 101, a gate driver 103, and a drain (data) driver 104. The display panel 101 has a plurality of scan lines (gate lines) G1, . . . , Gn, Gn+1, . . . , and Gm, a plurality of data lines (drain lines) D1, . . . , Dn, Dn+1, . . . , and Dm running perpendicular to the gate lines G1-Gm, and a plurality of pixels 102 provided at the intersections of the gate lines G1-Gm and the drain lines D1-Dm. The gate driver 103, which is connected to the gate lines G1-Gm, applies a gate signal (scan signal) to the gate lines G1-Gm. The drain driver 104, which is connected to the drain lines D1-Dm, applies a data signal (video signal) to the drain lines D1-Dm. Both of the gate driver 103 and the drain driver 104 form a peripheral drive circuit 105. Either one of the drivers 103 and 104 or both are preferably formed on the same substrate on which the display panel 101 is formed. The LCD is generally called a driver-integrated (driver-incorporated) LCD. The gate driver 103 or the drain driver 104 may be provided on both sides of the display panel 101.
FIG. 2 shows an equivalent circuit of one of the pixels 102. The pixel 102 includes a liquid crystal cell LC having a display electrode (pixel electrode) and a common electrode. The liquid crystal cell LC is connected to both a TFT 106 and a supplemental capacitor SC. The supplemental capacitor SC has a storage electrode and an opposing electrode. The TFT 106 has a gate connected to the gate line Gn, a drain connected to the drain line Dn, and a source connected to the display electrode of the liquid crystal cell LC and the storage electrode of the supplemental capacitor SC. The liquid crystal cell LC and the supplemental capacitor SC form a signal storage element. A voltage V.sub.com is applied to the common electrode of the liquid crystal cell LC. A predetermined voltage signal V.sub.R is applied to the opposing electrode of the supplemental capacitor SC. The common electrode of the liquid crystal cell LC is common to all of the pixels 102. The liquid crystal cell LC has a capacitor formed between the display electrode and the common electrode.
The writing characteristic and holding characteristic of the pixel 102 are important in improving the quality of displayed image. The writing characteristic shows how much the liquid crystal cell LC and the supplemental capacitor SC can write desired video signals per unit time based on the specifications of the display panel 101. The holding characteristic shows how long the written video signals can be held. The supplemental capacitor SC is provided to increase the capacitance of the pixel to improve the holding characteristic.
When a positive voltage is applied to the gate of the TFT 106 via the gate line Gn, the TFT 106 is turned on and a data signal is applied to the drain line Dn. As a result, the capacitor of the liquid crystal cell LC and the supplemental capacitor SC are charged. If a negative voltage is applied to the gate of the TFT 106, the TFT 106 is turned off. At this time, the capacitor of the liquid crystal cell LC and the supplemental capacitor SC hold the voltage applied to the drain line Dn. In other words, the pixel 102 holds a data signal as the data signal is applied to the associated one of the drain lines D1-Dm by controlling the voltage on the associated one of the gate lines G1-Gm. An image is displayed on the display panel 101 in accordance with the held data signal.
FIG. 3 is a cross-sectional view of a part of the conventional LCD display panel 101 which has polycrystalline silicon TFTs 106 of a bottom gate structure. It is preferable that the display panel 101 is of a transparent type. The method of manufacturing the display panel 101 will be discussed below.
Step 1 (see FIG. 4A): A chromium film 61 is formed on an insulator substrate 71 by sputtering.
Step 2 (see FIG. 4B): A resist pattern 62 for forming a gate electrode 76 and a supplemental capacitor electrode 77 is formed on the chromium film 61.
Step 3 (see FIG. 4C): With the resist pattern 62 used as an etching mask, the chromium film 61 is locally etched off by wet etching to form the gate electrode 76 and the supplemental capacitor electrode 77. At this time, the etching solution permeates the interfaces between both end portions of the resist pattern 62 and the chromium film 61, thereby forming undercuts 61a at parts of the chromium film 61 in the vicinity of both ends of the resist pattern 62. In cross section, therefore, the gate electrode 76 has a flat center portion (flat portion) 76a and a tapered end portion (tapered portion) 76b. The angle between the outer wall of the tapered portion 76b and the insulator substrate 71 is about 45.degree..
Step 4 (see FIG. 4D): A silicon nitride film 78, a silicon oxide film 79 and an amorphous silicon film 63 are formed in order on the gate and supplemental capacitor electrodes 76 and 77 and the insulator substrate 71 by plasma CVD (Chemical Vapor Deposition). The silicon nitride film 78 and the silicon oxide film 79 form a gate insulator film 80 in the region of the TFT 106, and form a dielectric film 84 in the region of the supplemental capacitor SC. Next, the device is annealed at 400.degree. C. to remove hydrogen from the amorphous silicon film 63 (dehydrogenation treatment). Then, excimer laser light is irradiated on the surface of the amorphous silicon film 63 to heat the film 63, thereby forming a polycrystalline silicon film 81. Such laser annealing using an excimer laser beam is called ELA (Excimer Laser Anneal). Then, a drain region 82, which includes low-concentration and high-concentration regions 82a and 82b, and a source region 83, which includes low-concentration and high-concentration regions 83a and 83b, are formed in the polycrystalline silicon film 81.
The tapered portion 76b of the gate electrode 76 is suitable for the withstanding voltage of the gate insulator film 80. That is, the tapered portion 76b prevents electrolytic concentration at the end portions of the gate electrode 76. The tapered portion 76b also improves the coverage of the gate insulator film 80 with respect to the both end portions of the gate electrode 76 to thereby allow the gate insulator film 80 to have a uniform thickness.
Because the gate electrode 76 is formed by the chromium film 61 which has a high thermal conductivity, heat escapes from the gate electrode 76 in the ELA process. The annealing temperature of a first portion of the amorphous silicon film 63 above the gate electrode 76 is lower than that of a second portion of the amorphous silicon film 63 above the insulator substrate 71. Since the degree of heat transfer of the tapered portion 76b is lower than that of the flat portion 76a, the annealing temperature of a third portion of the amorphous silicon film 63 above the flat portion 76a is lower than that of a fourth portion of the amorphous silicon film 63 above the tapered portion 76b. Therefore, the first portion of the amorphous silicon film 63 requires greater crystallization laser energy than the second portion. Further, the third portion of the amorphous silicon film 63 needs greater crystallization laser energy than the fourth portion.
High laser irradiation energy increases the grain size (crystal grain size) of the polycrystalline silicon film 81. Accordingly, a first portion of the polycrystalline silicon film 81 above the gate electrode 76 has a smaller grain size than a second portion of the polycrystalline silicon film 81 above the insulator substrate 71. Further, a third portion of the polycrystalline silicon film 81 above the flat portion 76a has a smaller grain size than a fourth portion of the polycrystalline silicon film 81 above the tapered portion 76b.
As shown in FIG. 3, a channel region 93 is defined in the third portion of the polycrystalline silicon film 81, the low-concentration regions 82a and 83a of the drain region 82 and source region 83 are defined in the fourth portion of the polycrystalline silicon film 81, and the high-concentration regions 82b and 83b of those regions 82 and 83 are defined in the second portion of the polycrystalline silicon film 81. The grain sizes thus become smaller in the order of the high-concentration regions 82b and 83b, the low-concentration regions 82a and 83a, and the channel region 93. The different grain sizes make it difficult to obtain a plurality of TFTs 106 with a uniform device characteristic, which degrades the quality of a displayed image.
In the formation of the tapered portion 76b using wet etching in step 3 (FIG. 4C), the angle between the outer wall of the tapered portion 76b and the insulator substrate 71 may vary. This is because, when the insulator substrate 71 of a relatively large size is used, different undercuts 61a appear at the associated portions of the insulator substrate 71. The different undercuts 61a are produced due to the difference between the temperatures of the etching solution at the center portion and end portions of the insulator substrate 71.
Such a variation in taper angle results in different thermal conductivities of the tapered portion 76b. Therefore, the annealing temperature, or the grain size, of a part of the amorphous silicon film 63 above the tapered portion 76b varies. This makes it difficult to acquire a plurality of TFTs 106 with a uniform device characteristic. Possible causes for the variation in grain size are (1) the attenuation of the ELA energy density caused by the inclined outer wall of the tapered portion 76b and (2) a local change in the state of the interface between the amorphous silicon film 63 and the gate insulator film 80.
It is an object of the present invention to provide thin film transistors which have a uniform device characteristic.